Backside Bus

A backside bus (BSB) was the dedicated communication pathway between a computer's CPU and its Level 2 (L2) cache. It was common in older processor architectures, before L2 cache was integrated directly onto the CPU die.

Early processors relied on two main buses:

• Frontside bus (FSB): Connected the CPU to main memory and the motherboard chipset.
• Backside bus (BSB): Provided a private, high-speed link between the CPU and its external L2 cache.

To avoid bottlenecks, the backside bus often ran at the same clock speed as the processor. It was often faster than the frontside bus, which typically operated at a lower frequency. As processor designs evolved, manufacturers moved the L2 (and later L3) cache onto the CPU itself, eliminating the need for a backside bus. Modern CPUs use internal cache interconnects and point-to-point links such as Intel’s QuickPath Interconnect (QPI) or AMD’s Infinity Fabric instead of traditional frontside and backside buses.